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WP217-无需板仿真即可估计实际的输出时序

消耗积分:0 | 格式:pdf | 大小:199 KB | 2012-02-16

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This document can help designers obtain moreaccurate I/O timing data without the need for boardlevelIBIS or SPICE simulations. Until recently, Xilinxspecified outputs into a lumped capacitive load.However, since rise and fall times force boardinterconnect to be considered transmission lines, alumped capacitive load is no longer relevant (see theTechXclusives document on this for more detail).Ideally, designers should simulate the interconnectsusing SPICE or IBIS with any of the commercialsimulators available.
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