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ADC08D1020,pdf datasheet (Low
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格式:rar |
大小:550 |
2009-10-10
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The ADC08D1020 is a dual, low power, high performance,
CMOS analog-to-digital converter that builds upon the ADC08D1000
platform. The ADC08D1020 digitizes signals to 8
bits of resolution at sample rates up to 1.3 GSPS. It has expanded
features compared to the ADC08D1000, which include
a test pattern output for system debug, a clock phase
adjust, and selectable output demultiplexer modes. Consuming
a typical 1.6 Watts in non-demultiplex mode at 1 GSPS
from a single 1.9 Volt supply, this device is guaranteed to have
no missing codes over the full operating temperature range.
The unique folding and interpolating architecture, the fully differential
comparator design, the innovative design of the internal
sample-and-hold amplifier and the calibration schemes
enable a very flat response of all dynamic parameters beyond
Nyquist, producing a high 7.4 Effective Number of Bits
(ENOB) with a 498 MHz input signal and a 1 GHz sample rate
while providing a 10−18 Code Error Rate (C.E.R.) Output formatting
is offset binary and the Low Voltage Differential Signaling
(LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V.
CMOS analog-to-digital converter that builds upon the ADC08D1000
platform. The ADC08D1020 digitizes signals to 8
bits of resolution at sample rates up to 1.3 GSPS. It has expanded
features compared to the ADC08D1000, which include
a test pattern output for system debug, a clock phase
adjust, and selectable output demultiplexer modes. Consuming
a typical 1.6 Watts in non-demultiplex mode at 1 GSPS
from a single 1.9 Volt supply, this device is guaranteed to have
no missing codes over the full operating temperature range.
The unique folding and interpolating architecture, the fully differential
comparator design, the innovative design of the internal
sample-and-hold amplifier and the calibration schemes
enable a very flat response of all dynamic parameters beyond
Nyquist, producing a high 7.4 Effective Number of Bits
(ENOB) with a 498 MHz input signal and a 1 GHz sample rate
while providing a 10−18 Code Error Rate (C.E.R.) Output formatting
is offset binary and the Low Voltage Differential Signaling
(LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V.
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