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GPON基础灵活的时钟转换器SDH和以太网ad9553数据表
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The AD9553 is a phase-locked loop （PLL） based clock translator designed to address the needs of passive optical networks （PON） and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input. The AD9553 is pin programmable， providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs （OUT1 and OUT2）。 The device also has a 3-wire SPI interface， enabling the user to program custom input-to-output frequency translations. The AD9553 output drivers are compatible with LVPECL， LVDS， or single-ended CMOS logic levels， although the AD9553 is implemented in a strictly CMOS process. The AD9553 operates over the extended industrial temperature range of −40°C to +85°C.
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