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74ACT11543,pdf(Octal Registere
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This 8-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (
or ) and output enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable () input must be low in order to enter data from A or to output data to B. Having low and low makes the A-to-B latches transparent; a subsequent low-to-high transition of puts the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B-to-A is similar, but requires the use of , , and inputs.
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