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MAX5894 pdf datasheet
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大小:333 |
2008-12-18
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The MAX5894 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single-carrier transmit applica-
tions. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 14-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 86dBc while consuming 1.1W.
The device also delivers 73dB ACLR for two-carrier
WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
The MAX5894 features a fIM/4 digital image-reject mod-
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/2 or fIM/4.
The MAX5894 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
ters, fIM/2, fIM/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single-carrier transmit applica-
tions. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 14-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 86dBc while consuming 1.1W.
The device also delivers 73dB ACLR for two-carrier
WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
The MAX5894 features a fIM/4 digital image-reject mod-
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/2 or fIM/4.
The MAX5894 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
ters, fIM/2, fIM/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
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