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dssha1综合SHA-1协处理器
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Description
The DSSHA1 is a synthesizable， memory-mapped SHA-1 coprocessor that includes a 64-byte general-purpose RAM that stores the 64-byte message. The input message is used to compute the SHA-1 MAC. The DSSHA1 input and output port signals are designed to internally connect to a 32-bit bus. By a positive comparison result， authentication security is achieved between a host system and slave accessories.
Figure1 shows the DSSHA1 block diagram. Table 1 describes the signals that connect the DSSHA1 to the host system. Using the data bus input， address， and control signals， the 64-byte SHA-1 message is inserted into the RAM. Triggering the input signal RUN_SHA to logic-high starts the SHA-1 computation. The output BUSY signal indicates an occurring computation. Upon completion of the BUSY signal， the result registers contain the 20-byte message digest for reading.
The DSSHA1 performs the job of a SHA-1 engine. The input buffer accepts the message. The MAC output buffer receives the resultant SHA-1 computation. Figure 2 illustrates data flow into and out of the SHA-1 engine.
Applying a power reset initiates the first step of using the SHA-1 engine. Next， a message is loaded into the input buffer in the format of Table 3. Upon completion of a message load， the user pulses the RUN_SHA input signal. For the duration of the SHA-1 computation， the BUSY signal goes and remains logic-high. A BUSY signal goes logic-low again when the SHA-1 computation completes. All five of the MRR registers （see Table 4） contain the MAC result for reading.
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