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cmos,16位468.75千赫AD7721模数转换器
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The AD7721 is a complete low power， 12-/16-bit， sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input of 0 V to 2.5 V or ±1.25 V. The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-andhold circuitry. The modulator output is processed by two finite impulse response （FIR） digital filters in series. The on-chip filtering reduces the external antialias requirements to first order in most cases. Settling time for a step input is 97.07 µs while the group delay for the filter is 48.53 µs when the master clock equals 15 MHz. The AD7721 can be operated with input bandwidths up to 229.2 kHz. The corresponding output word rate is 468.75 kHz. The part can be operated with lower clock frequencies also. The sample rate， filter corner frequency and output word rate will be reduced also， as these are proportional to the external clock frequency. The maximum clock frequencies in parallel mode and serial mode are 10 MHz and 15 MHz respectively.
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