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74HC356 pdf datasheet
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2008-08-06
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MM54HC354/MM74HC354/
MM54HC356/MM74HC356
8-Channel TRI-STATEÉ Multiplexers with Latches
General Description
The MM54HC354/MM74HC354 and MM54HC356/
MM74HC356 utilize advanced silicon-gate CMOS technology.
They exhibit the high noise immunity and low power dissipation
of standard CMOS integrated circuits, along with
the ability to drive 15 LS-TTL loads. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized
system.
These data selectors/multiplexers contain full on-chip binary
decoding to select one of eight data sources. The data
select address is stored in transparent latches that are enabled
by a low level address on pin 11, SC. Data on the 8
input lines is stored in a parallel input/output register which
in the MM54HC354/MM74HC354 is composed of 8 transparent
latches enabled by a low level on pin 9, DC, and in
the MM54HC356/MM74HC356 is composed of 8 edge-triggered
flip-flops, clocked by a low to high transition on pin 9,
CLK. Both true (Y) and complementary (W) TRI-STATE outputs
are available on both devices.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS-TTL logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
Y Transparent latches on data select inputs
Y Choice of data registers:
Transparent ('354)
Edge-triggered ('356)
Y TRI-STATE complementary outputs with fanout
of 15 LS-TTL loads
Y Typical propagation delay:
Data to output ('354): 32 ns
Clock to output ('346): 35 ns
Y Wide power supply range: 2V±6V
Y Low quiescent supply current: 80 mA maximum
Y Low input current: 1 mA maximum
MM54HC356/MM74HC356
8-Channel TRI-STATEÉ Multiplexers with Latches
General Description
The MM54HC354/MM74HC354 and MM54HC356/
MM74HC356 utilize advanced silicon-gate CMOS technology.
They exhibit the high noise immunity and low power dissipation
of standard CMOS integrated circuits, along with
the ability to drive 15 LS-TTL loads. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized
system.
These data selectors/multiplexers contain full on-chip binary
decoding to select one of eight data sources. The data
select address is stored in transparent latches that are enabled
by a low level address on pin 11, SC. Data on the 8
input lines is stored in a parallel input/output register which
in the MM54HC354/MM74HC354 is composed of 8 transparent
latches enabled by a low level on pin 9, DC, and in
the MM54HC356/MM74HC356 is composed of 8 edge-triggered
flip-flops, clocked by a low to high transition on pin 9,
CLK. Both true (Y) and complementary (W) TRI-STATE outputs
are available on both devices.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS-TTL logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
Y Transparent latches on data select inputs
Y Choice of data registers:
Transparent ('354)
Edge-triggered ('356)
Y TRI-STATE complementary outputs with fanout
of 15 LS-TTL loads
Y Typical propagation delay:
Data to output ('354): 32 ns
Clock to output ('346): 35 ns
Y Wide power supply range: 2V±6V
Y Low quiescent supply current: 80 mA maximum
Y Low input current: 1 mA maximum
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