资料下载
×
74LS191 pdf datasheet
消耗积分:10 |
格式:rar |
大小:133 |
2008-08-06
其实znvm
分享资料个
DM54LS190/DM74LS190, DM54LS191/DM74LS191
Synchronous 4-Bit Up/Down Counters with Mode Control
General Description
These circuits are synchronous, reversible, up/down counters.
The LS191 is a 4-bit binary counter and the LS190 is a
BCD counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously, so that the outputs
change simultaneously when so instructed by the steering
logic. This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple clock)
counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting.
Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
These counters are fully programmable; that is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input.
This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the
preset inputs.
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the number
of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish
look-ahead for high-speed operation.
Synchronous 4-Bit Up/Down Counters with Mode Control
General Description
These circuits are synchronous, reversible, up/down counters.
The LS191 is a 4-bit binary counter and the LS190 is a
BCD counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously, so that the outputs
change simultaneously when so instructed by the steering
logic. This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple clock)
counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting.
Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
These counters are fully programmable; that is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input.
This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the
preset inputs.
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the number
of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish
look-ahead for high-speed operation.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
