资料下载
CD54HC259,CD74HC259,CD54HCT259
李敏
分享资料个
The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.
This latches three active modes and one reset mode. When both the Latch Enable (LE\) and Master Reset (MR\) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR\ and LE\ are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (Addressable Latch mode) allows the addressed latch’s output to follow the data input; all other latches are unaffected.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
