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74HC165 pdf datasheet
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大小:133 |
2008-08-06
靓仔峰
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MM54HC165/MM74HC165
Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM54HC165/MM74HC165 high speed PARALLEL-IN/
SERIAL-OUT SHIFT REGISTER utilizes advanced silicongate
CMOS technology. It has the low power consumption
and high noise immunity of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from QA to QH when
clocked. Parallel inputs to each stage are enabled by a low
level at the SHIFT/LOAD input. Also included is a gated
CLOCK input and a complementary output from the eighth
bit.
Clocking is accomplished through a 2-input NOR gate permitting
one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel loading
is inhibited as long as the SHIFT/LOAD input is high.
When taken low, data at the parallel inputs is loaded directly
into the register independent of the state of the clock.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM54HC165/MM74HC165 high speed PARALLEL-IN/
SERIAL-OUT SHIFT REGISTER utilizes advanced silicongate
CMOS technology. It has the low power consumption
and high noise immunity of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from QA to QH when
clocked. Parallel inputs to each stage are enabled by a low
level at the SHIFT/LOAD input. Also included is a gated
CLOCK input and a complementary output from the eighth
bit.
Clocking is accomplished through a 2-input NOR gate permitting
one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel loading
is inhibited as long as the SHIFT/LOAD input is high.
When taken low, data at the parallel inputs is loaded directly
into the register independent of the state of the clock.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
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