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AD9575,pdf daasheet(Network Cl
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2010-01-26
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The AD9575 provides a highly integrated, dual output clockgenerator function including an on-chip PLL core that isoptimized for network clocking. The integer-N PLL design isbased on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize linecard performance. Other applications with demanding phase
noise and jitter requirements also benefit from this part.The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltage
controlled oscillator (VCO), and pin selectable feedback and output dividers.
noise and jitter requirements also benefit from this part.The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltage
controlled oscillator (VCO), and pin selectable feedback and output dividers.
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