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Interfacing DDR &DDR2 SDRAM wi
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2009-03-28
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DDR SDRAM is a 2n prefetch architecture with two data transfers per
clock cycle. In the 2n prefetch architecture, two data words are fetched
from the memory array during a single read command. DDR SDRAM
uses a strobe signal (DQS) that is associated with a group of data pins
(DQ) for read and write operations. Both the DQS and DQ ports are
bidirectional. Address ports are shared for write and read operations.
Write and read operations are sent in bursts, and DDR SDRAM supports
burst lengths of two, four, and eight. This means that you need to provide
2, 4, or 8 groups of data for each write transaction, and you receive two,
four, or eight of data for each read transaction. The interval between the
time the read command is clocked into the memory and the time the data
is presented at the memory pins is called the column address strobe
(CAS) latency. DDR SDRAM supports CAS latencies of 2, 2.5, and 3,
depending on the operating frequency. Both the burst length and CAS
latency are set in the DDR SDRAM mode register.
DDR SDRAM specifies the use of the SSTL-2 I/O standard. Each DDR
SDRAM device is divided into four banks, and each bank has a fixed
number of rows and columns and can hold between 64 Mb to 1 Gb of
data. Only one row per bank can be accessed at one time. The ACTIVE
command opens a row and the PRECHARGE command closes a row.
DDR2 SDRAM
DDR2 SDRAM is the second generation of the DDR SDRAM memory
standard. DDR2 SDRAM is a 4n prefetch architecture with two data
transfers per clock cycle. In the 4n prefetch architecture, four data words
are fetched from the memory array during a single read command. DDR2
SDRAM uses a DQS that is associated with a group DQs for read and
write operations. Both the DQS and DQ ports are bidirectional. Address
ports are shared for write and read operations.
clock cycle. In the 2n prefetch architecture, two data words are fetched
from the memory array during a single read command. DDR SDRAM
uses a strobe signal (DQS) that is associated with a group of data pins
(DQ) for read and write operations. Both the DQS and DQ ports are
bidirectional. Address ports are shared for write and read operations.
Write and read operations are sent in bursts, and DDR SDRAM supports
burst lengths of two, four, and eight. This means that you need to provide
2, 4, or 8 groups of data for each write transaction, and you receive two,
four, or eight of data for each read transaction. The interval between the
time the read command is clocked into the memory and the time the data
is presented at the memory pins is called the column address strobe
(CAS) latency. DDR SDRAM supports CAS latencies of 2, 2.5, and 3,
depending on the operating frequency. Both the burst length and CAS
latency are set in the DDR SDRAM mode register.
DDR SDRAM specifies the use of the SSTL-2 I/O standard. Each DDR
SDRAM device is divided into four banks, and each bank has a fixed
number of rows and columns and can hold between 64 Mb to 1 Gb of
data. Only one row per bank can be accessed at one time. The ACTIVE
command opens a row and the PRECHARGE command closes a row.
DDR2 SDRAM
DDR2 SDRAM is the second generation of the DDR SDRAM memory
standard. DDR2 SDRAM is a 4n prefetch architecture with two data
transfers per clock cycle. In the 4n prefetch architecture, four data words
are fetched from the memory array during a single read command. DDR2
SDRAM uses a DQS that is associated with a group DQs for read and
write operations. Both the DQS and DQ ports are bidirectional. Address
ports are shared for write and read operations.
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