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用MPC106对寄存式SDRAM模块进行控制
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2009-06-30
刘伟
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In this document, the term ÔMPC106Õ is used as an abbreviation for the phrase ÔMPC106
PCI bridge/memory controllerÕ. Also, the term Ô60xÕ is used to denote a 32-bit
microprocessor from the PowerPCª architecture family that conforms to the bus interface
of the PowerPC 603ª, PowerPC 604ª, or PowerPC 750ª microprocessors. 60x
processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,
and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).
This document contains the following topics:
Topic Page
Section 1.1, ÒIntroductionÓ 2
Section 1.2, ÒBackgroundÓ 2
Section 1.3, ÒRead CyclesÓ 3
Section 1.4, ÒWrite CyclesÓ 5
Section 1.5, ÒExampleÓ 9
Section 1.6, ÒSummaryÓ 10
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/SPS/PowerPC/.
PCI bridge/memory controllerÕ. Also, the term Ô60xÕ is used to denote a 32-bit
microprocessor from the PowerPCª architecture family that conforms to the bus interface
of the PowerPC 603ª, PowerPC 604ª, or PowerPC 750ª microprocessors. 60x
processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,
and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).
This document contains the following topics:
Topic Page
Section 1.1, ÒIntroductionÓ 2
Section 1.2, ÒBackgroundÓ 2
Section 1.3, ÒRead CyclesÓ 3
Section 1.4, ÒWrite CyclesÓ 5
Section 1.5, ÒExampleÓ 9
Section 1.6, ÒSummaryÓ 10
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/SPS/PowerPC/.
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