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74LS193 pdf datasheet
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2008-08-06
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54LS193/DM54LS193/DM74LS193
Synchronous 4-Bit Up/Down Binary
Counters with Dual Clock
General Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so that the outputs change together
when so instructed by the steering logic. This mode of
operation eliminates the output counting spikes normally associated
with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input.
The direction of counting is determined by which count input
is pulsed while the other count input is held high.
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is low. The output will change
independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying
the count length with the preset inputs.
A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.
Similarly, the carry output produces a pulse equal in width to
the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.
Synchronous 4-Bit Up/Down Binary
Counters with Dual Clock
General Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so that the outputs change together
when so instructed by the steering logic. This mode of
operation eliminates the output counting spikes normally associated
with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input.
The direction of counting is determined by which count input
is pulsed while the other count input is held high.
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is low. The output will change
independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying
the count length with the preset inputs.
A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.
Similarly, the carry output produces a pulse equal in width to
the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.
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2012-11-23
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