资料下载
×
SN54AHCT594, SN74AHCT594,pdf(8
消耗积分:2 |
格式:rar |
大小:660 |
2010-08-03
分享资料个
The ’AHCT594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SRCLR\, RCLR\) inputs are provided on both the shift and storage registers. A serial (QH’) output is provided for cascading purposes.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
