82527串行通信控制器结构综述

1.0 GENERAL FEATURES ................ 1
1.1 Functional Overview ............... 2
1.2 CAN Controller ..................... 3
1.3 RAM ................................ 3
1.4 CPU Interface Logic ................. 3
1.5 Clockout ............................ 3
1.6 Two 8-Bit Ports ...................... 3
2.0 PACKAGE DIAGRAM/PIN OUT ..... 4
3.0 PIN DESCRIPTION ................ 5
3.1 Hardware Reset ..................... 8
3.2 Software Initialization .............. 8
4.0 FUNCTIONAL DESCRIPTION ....... 8
4.1 82527 Address Map .............. 9
4.2 Control Register (00H) .............. 9
4.3 Status Register (01H) ................10
4.4 CPU Interface Register (02H) ...... 12
4.5 Clocking Description ................ 13
4.6 High Speed Read Register
(04±05H) .......................... 13
4.7 Global Mask - Standard Register
(06±07H) ............................ 14
4.8 Global Mask - Extended Register
(08±0BH) ............................ 14
4.9 Acceptance Filtering
Implications ........................... 15
4.10 Message 15 Mask Register
(0C±0FH) ............................... 15
4.11 CLKOUT Register (1FH) ........... 15
4.12 Bus Configuration Register
(2FH) .......................... 16
4.13 Bit Timing Overview .............. 16
4.14 Bit Timing Registers
(3FH, 4FH) ................................. 18
4.15 Comparison of 82526 and 82527
Bit Timing Calculations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19
4.16 Interrupt Register (5FH) ......... 19
4.17 Serial Reset Address (FFH) ....... 20
4.18 82527 Message Objects ............ 20
4.19 Control 0 and Control 1
Registers ................................ 21
4.20 Arbitration 0, 1, 2, 3 Registers .... 23
CONTENTS PAGE
4.21 Message Configuration
Register ............................ 24
4.22 Data Bytes ..................... 24
4.23 Special Treatment of Message
Object 15 ........................... 24
5.0 PORT REGISTERS .................. 25
6.0 SERIAL RESET ADDRESS (FFH) ...... 26
7.0 FLOW DIAGRAMS ................... 26
7.1 82527 Handling of Message
Objects 1-14 (Direction e
Transmit) ........................... 27
7.2 82527 Handling of Message
Objects 1-14 (Direction e
Receive) ............................ 28
7.3 CPU Handling of Message Object
15 (Direction e Receive) ............ 29
7.4 CPU Handling of Message Objects
1±14 (Direction e Transmit) ........ 30
7.5 CPU Handling of Message Objects
1±14 (Direction e Receive) ......... 31
8.0 CPU Interface Logic ............. 32
8.1 Serial Control Byte ............. 34
9.0 82527 FRAME TYPES ............... 35
9.1 Data Frame ...................... 35
9.2 Remote Frame .................... 36
9.3 Error Frame ..................... 36
9.4 Overload Frame .................. 37
9.5 Coding/Decoding ................. 38
9.6 Arbitration ..................... 38
10.0 ERROR DETECTION AND
CONFINEMENT ......................... 39
10.1 Bit Error ...................... 39
10.2 Bit Stuffing Error ............. 39
10.3 CRC Error ...................... 39
10.4 Form Error ......................39
10.5 Error Detection Capabilities ... 40
10.6 Error Confinement .............. 40
10.7 82527 States With Respect to the
Serial Bus .......................... 40
11.0 SAMPLE PROGRAM ................. 41