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ADC08D500,pdf datasheet (High
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大小:551 |
2009-10-10
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The ADC08D500 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 800 MSPS. Consuming
a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and interpolating
architecture, the fully differential comparator design,
the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, producing
a high 7.5 ENOB with a 250 MHz input signal and a 500
MHz sample rate while providing a 10-18 B.E.R. Output formatting
is offset binary and the LVDS digital outputs are
compatible with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 1 GSPS ADC.
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 800 MSPS. Consuming
a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and interpolating
architecture, the fully differential comparator design,
the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, producing
a high 7.5 ENOB with a 250 MHz input signal and a 500
MHz sample rate while providing a 10-18 B.E.R. Output formatting
is offset binary and the LVDS digital outputs are
compatible with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 1 GSPS ADC.
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