资料下载
×
DS92LV18,pdf datasheet (18-Bit
消耗积分:5 |
格式:rar |
大小:556 |
2009-10-14
张龙祥
分享资料个
The DS92LV18 Serializer/Deserializer (SERDES) pair transparently
translates a 18–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 18-bit, or less, bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by narrowing
data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
translates a 18–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 18-bit, or less, bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by narrowing
data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
