资料下载
cy7c09369v/89v同步双端口静态ram
分享资料个
Features True dual-ported memory cells that allow simultaneous access of the same memory location Six flow through/pipelined devices： ❐ 16K × 16 / 18 organization （CY7C09269V/369V） ❐ 32K × 16 organization （CY7C09279V） ❐ 64K × 16 / 18 organization （CY7C09289V/389V） Three modes： Flow through Pipelined Burst Pipelined output mode on both ports allows fast 100 MHz operation 0.35 micron CMOS for optimum speed and power High speed clock to data access： 7.5［1］， 9， 12 ns （max） 3.3 V low operating power：
❐ Active = 115 mA （typical） ❐ Standby = 10 A （typical） ■ Fully synchronous interface for easier operation ■ Burst counters increment addresses internally： ❐ Shorten cycle times ❐ Minimize bus noise ❐ Supported in flow through and pipelined modes ■ Dual chip enables easy depth expansion ■ Upper and lower byte controls for bus matching ■ Automatic power down ■ Commercial and industrial temperature ranges ■ Pb-free 100-pin TQFP package available Functional Description For a complete list of related documentation， click here.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
