资料下载
SN74SSTL16857,pdf(14-Bit SSTL_
远不及你
分享资料个
This 14-bit registered buffer is designed for 2.3-V to 3.6-V VCC operation and SSTL_2 data input and output levels.
All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET\) input. All outputs are SSTL_2, Class II compatible.
When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
The SN74SSTL16857 is characterized for operation from 0°C to 70°C.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
