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The Verilog Hardware Descripti
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The Verilog language is a hardware description language that provides a means of
specifying a digital system at a wide range of levels of abstraction. The language supports
the early conceptual stages of design with its behavioral level of abstraction, and
the later implementation stages with its structural abstractions. The language includes
hierarchical constructs, allowing the designer to control a description’s complexity.
Verilog was originally designed in the winter of 1983/84 as a proprietary verification/
simulation product. Later, several other proprietary analysis tools were developed
around the language, including a fault simulator and a timing analyzer. More recently,
Verilog has also provided the input specification for logic and behavioral synthesis
tools. The Verilog language has been instrumental in providing consistency across
these tools. The language was originally standardized as IEEE standard #1364-1995.
It has recently been revised and standardized as IEEE standard #1364-2001. This
book presents this latest revision of the language, providing material for the beginning
student and advanced user of the language.
It is sometimes difficult to separate the language from the simulator tool because
the dynamic aspects of the language are defined by the way the simulator works. Further,
it is difficult to separate it from a synthesis tool because the semantics of the language
become limited by what a synthesis tool allows in its input specification and
produces as an implementation. Where possible, we have stayed away from simulatorand
synthesis-specific details and concentrated on design specification. But, we have
included enough information to be able to write working executable models.
Verilog –A Tutorial Introduction 1
Getting Started
A Structural Description
Simulating the binaryToESeg Driver
Creating Ports For the Module
Creating a Testbench For a Module
Behavioral Modeling of Combinational Circuits
Procedural Models
Rules for Synthesizing Combinational Circuits
Procedural Modeling of Clocked Sequential Circuits
Modeling Finite State Machines
Rules for Synthesizing Sequential Systems
Non-Blocking Assignment ("<=")
Module Hierarchy
The Counter
A Clock for the System
Tying the Whole Circuit Together
Tying Behavioral and Structural Models Together
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