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SN74HC273-Q1,pdf(Octal D-Type
消耗积分:3 |
格式:rar |
大小:206 |
2010-07-29
刘埃生
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This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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