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ICS9DB102 pdf datasheet (2 Out

消耗积分:5 | 格式:rar | 大小:343 | 2008-08-06

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The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It
attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock
request (OE#) pins make the ICS9DB102 suitable for Express Card applications.

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