×

SN74SSTU32866A,pdf(25-Bit Conf

消耗积分:5 | 格式:rar | 大小:821 | 2010-08-19

陈文博

分享资料个

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only 1 device per DIMM is required to drive 9 SDRAM loads. In the 1:2 pinout configuration, 2 devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output.

The SN74SSTU32866A buffer operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK\ going low.

The SN74SSTU32866A buffer accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1=1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low).

声明:本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人,不代表电子发烧友网立场。文章及其配图仅供工程师学习之用,如有内容侵权或者其他违规问题,请联系本站处理。 举报投诉

评论(0)
发评论

下载排行榜

全部0条评论

快来发表一下你的评论吧 !