资料下载
HFAN-04.5.5评估电源噪声抑制比对PLL时钟合成器的
分享资料个
HFAN-04.5.5评估电源噪声抑制比对PLL时钟合成器的影响
Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers
This application note discusses the effects of powersupply
noise interference on PLL-based clock
generators. It describes several measurement
techniques for evaluating the resulting DJ
(deterministic jitter). Relationships are derived
outlining how frequency-domain spur measurements
can be used to evaluate timing jitter behavior.
Laboratory bench-test results are used to compare
the approaches, and demonstrate how to reliably
assess the PSNR (power-supply noise rejection)
performance of a reference clock generator
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
