资料下载
SN74ALVCH16901,pdf(18-BIT UNIV
分享资料个
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or CLKENBA\) inputs. It also provides parity-enable (SEL\) and parity-select (ODD/EVEN\) inputs and separate error-signal (ERRA\ or ERRB\) outputs for checking parity. The direction of data flow is controlled by OEAB\ and OEBA\. When SEL\ is low, the parity functions are enabled.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
