资料下载
SN54BCT29825,SN74BCT29825,pdf(
385288
分享资料个
These 8-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The eight flip-flops are edge-triggered D-type flip-flops. With the clock-enable (
) input low, the device enters data on the low-to-high transition of the clock. Taking high disables the clock buffer, thus latching the outputs. Taking the clear () input low causes the eight Q outputs to go low independently of the clock.
Buffered output-enable (,, or) inputs can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
