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SN74SSTV32867,pdf(26-Bit Regis
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This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.
The SN74SSTV32867 operates from a differential clock (CLK and CLK)\. Data are registered at the crossing of CLK going high and CLK\ going low.
The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ always must be held at a valid logic high or low level.
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