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DS90UR905Q/DS90UR906Q,pdf data
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2009-10-14
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The DS90UR905Q/906Q chipset translates a parallel RGB
Video Interface into a high-speed serialized interface over a
single pair. This serial bus scheme greatly eases system design
by eliminating skew problems between clock and data,
reduces the number of connector pins, reduces the interconnect
size, weight, and cost, and overall eases PCB layout. In
addition, internal DC balanced decoding is used to support
AC-coupled interconnects.
Video Interface into a high-speed serialized interface over a
single pair. This serial bus scheme greatly eases system design
by eliminating skew problems between clock and data,
reduces the number of connector pins, reduces the interconnect
size, weight, and cost, and overall eases PCB layout. In
addition, internal DC balanced decoding is used to support
AC-coupled interconnects.
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