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DS90C363/DS90CF364,pdf datashe
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2009-10-14
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The DS90C363 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF364 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data throughputs
is 170 Mbytes/sec. The Transmitter is offered with programmable
edge data strobes for convenient interface with a
variety of graphics controllers. The Transmitter can be programmed
for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge Transmitter will interoperate
with a Falling edge Receiver (DS90CF364) without
any translation logic.
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF364 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data throughputs
is 170 Mbytes/sec. The Transmitter is offered with programmable
edge data strobes for convenient interface with a
variety of graphics controllers. The Transmitter can be programmed
for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge Transmitter will interoperate
with a Falling edge Receiver (DS90CF364) without
any translation logic.
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